The present invention relates to computer-controlled pinball games, and more particularly, to a matrix address decoder for use with such games.
Typically, pinball games employ microprocessors to control operation of various game functions, such as activation of lamps and solenoids in response to pinball-activated switches disposed on the playfield. The microprocessor can also operate score displays based on inputs from these switches. The lamps and playfield features are often designated by sequential numbers for identification. Status information about these playfield features, such as whether the playfield feature is activated or not, is kept in a block of sequential locations in system memory, with each bit of each memory location representing status information about a different one of the specifically numbered playfield features. Similarly, information about the status of the playfield switches, whether electrically open or closed, is kept in a different block of memory. The switches are also sequentially numbered, and each bit of the memory matrix contains the status of a specific one of the switches.
The memory arrays containing information about the playfield features and switches may be thought of as being organized in matrix format, with each bit position in a given memory location corresponding to a column and each successive memory address corresponding to a row location. Information is normally stored in the matrix in a sequence determined by the sequential numbers assigned to the playfield features or switches. For example, the first byte of the information matrix (the byte located at the beginning address) contains information bits corresponding to playfield features or switches numbered one through eight. The next successive memory location contains the information for switches or playfield features nine through 16. Thus, information about a specific playfield feature or switch may be accessed by the system microprocessor if both the sequential number assigned to the switch or playfield feature and the starting memory address of the information matrix are known.
In the course of game play, the system microprocessor must translate the sequential number assigned to a playfield feature or switch in order to access the memory location containing the information for the proper device. This task is a matter of simple mathematical calculation, which the microprocessor can perform. However, manipulation of these bits of status information can consume a substantial portion of the microprocessor's time, limiting the time available for other important tasks. As the number of playfield features and switches increases, the amount of processing time spent performing these decoding computations also increases, further reducing the amount of processing time available for other operations.
It is desirable to relieve the system microprocessor of the need to perform repetitive manipulations of data to obtain status information about playfield features and switches. One possible solution would be to include a separate co-processor having full processing capabilities. But this would be relatively expensive to implement and would needlessly increase the complexity of the pinball game operating system. Another option would be to use a look-up table for relating the sequential number of the playfield features and switches to the corresponding memory location and bit position. But this option would also require a substantial amount of processing time. The system would still be subject to limitations of efficiency.
Accordingly, it is an object of the invention to provide a dedicated matrix address decoder to decode the memory location and bit position of status information relating to a specific playfield feature or switch when both the sequential number of the device for which information is sought and the starting address for the information matrix are known.
It is another object of the invention to provide such a dedicated matrix address decoder requiring a minimum of communication with the main microprocessor.
It is a further object of the invention to provide such a matrix address decoder which is implemented at low cost and without unnecessarily expanding game complexity.
These objects, as well as others, will become apparent to those skilled in the art from the detailed description of the invention provided below.